High-speed serial interfaces such as CEI, XFP/XFI, 10-Gbit/s Ethernet, and both 4-Gbit/s and 10-Gbit/s Fibre Channel are creating demands for test equipment that can give you detailed performance ...
Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...
The eye diagram is probably the most well-known signal integrity tool because it combines numerous signal integrity characteristics such as rise/fall, overshoot/undershoot, and voltage/jitter into a ...
The potential causes of signal integrity problems in a device are wide ranging, including the physical layout of the design, underperforming components, and accumulative affects with multiple causes.
Learn more with our material for efficient eye diagram testing in DDR3/DDR4 system designs. Compliance testing is essential to ensuring that dynamic random access memory (DRAM) signals meet the JEDEC ...
Today’s high-end field programmable gate arrays (FPGAs) with embedded transceivers support a variety of widely accepted serial protocol standards, including Gigabit Ethernet, PCI Express, XAUI and ...
Close cooperation between Apache, ERNI, and Xilinx allow S-parameter analysis of chip-to-chip, board-to-board and backplane designs SAN JOSE, Calif., February 11, 2004 — Apache Design Solutions and ...
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